Lychee HEX ZYNQ7020 FPGA Development Board Raspberry Pie Edition XILINX ZEDBOARD

Description

1.1 main module
1) FPGA: Zynq XC7Z020
2) NAND Flash: 2Gb
3) LPDDR3: 1GB
4) 100M network port: x1
5) USB 2.0: x4
6) TF card slot: x1
2.1 Introduction of main chips:
2.1.1 Main chip: XC7Z020-1CLG484
The Zynq®-7000 SoC family integrates the software programmability of the ARM® processor with the hardware programmability of the FPGA for not only critical analysis and hardware acceleration, but also high CPU, DSP, ASSP and mixed-signal functions on a single device .
This development board uses chip specific features:
PS section:
Cortex-A9, dual core 667MHz,
L1: 32KB instruction space, 32KB data space per core, L2: 512KB, on-chip memory space 256KB.
PL part:
Artix-7 FPGA, programmable logic unit: 85K,
LUTs: 53200, Block RAM: 4.9Mb
2.1.2 Memory Chip: MT41K256M16TW-107
Capacity: 512MB; 32Meg x 16 x8 banks.
DDR3L SDRAM (1.35V), upward compatible 1.5V
2.1.3 NAND FLASH Memory Chip: MT29F2G08ABAEAWP
1) ONFI 1.0 interface standard
2) SLC technology
3) Structure:
Page size x8
2112 bytes (2048+64bytes)
Block size
64 pages (128K + 4K bytes)
Plane size
2 planes x 1024 blocks per plane
Device size
2Gb: 2048 blocks
2.1.4 ULPI Bridge: USB3320C
The USB3320 is a highly integrated, full-featured Hi-Speed USB 2.0 transceiver based on the Microchip ULPI interface.
2.1.5 USB HUB & 10/100 NIC chip: LAN9514-JZX
USB Hub:
1 x upstream USB2.0 PHY, 4 x downstream USB2.0 PHY
Network card:
Integrated MAC and PHY with support for 10BASE-T and 100BASE-TX
3, lychee sugar HAX development board use:
3.1 Routine application
Method 1: Write the BIN binary file to the SD card. Power on loading;
Method 2: The Vivado project compiles the generated .out file and downloads it via JTAG;
Achieve the effect:
The LED light is constantly flashing. The other one is controlled by the button.
The process is as follows:
1) New project under ISE:
2) Instantiation
3) Launch SDK
4) Application Project
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